IP P&R CAD Methodology Principal-Stuff


Penang, Malaysia

Position Type

Full Time

About Us

At RapidSilicon, we focus on bringing creativity to FPGA design by combining open-source FPGA methodology with proprietary technologies that enable a faster design-to-silicon turnaround. Our employees work on innovative AI-enhanced EDA tools to provide the most optimized design result that satisfies the needs in general-purpose or domain-specific applications.

To view our job listings, please visit our Careers page at rapidsilicon.com/careers/

Job Description

The IP Design and Frontend Principal CAD Engineer will set the technical direction of CAD Design Methodology for the global IP P&R team

  • Responsible for RTL to GDS CAD Flow and Design Methodology from front to backend of VLSI design at the IP/SS level
  • Deliver design flow and methodology for the internal team
  • Establish high quality delivery culture across global IP team

Minimum Qualifications

  • B.S. in EE/CE/CS (M.S. preferred)
  • 12 years in chip development, 6 of those years P&R
  • 3 years using a scripting language, such as Tcl or Python
  • Experience coordinating projects and developing talent between local and remote teams
  • Understands contemporary manufacturing design rules

Preferred Skills

  • Developed IC Design Flow and Methodology: AMS, RTL to GDS floe including, RTL, STA, PnR, Formal Verification, Extraction, Power, EMIR, DFT, ATPG, Physical Verification, etc.
  • Developed an FPGA design flow; used an FPGA product
  • Understanding of packaging co-design and DFX flows
  • Have setup PnR, STA, EMIR, DFT, ATPG, LVS/DRC, DFM, and reliability checks

Deadline to Apply

Drop us an email, with attached resume, to careers@rapidsilicon.com
*We’re an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status