Sr. Manager, Physical Design Location Los Gatos, CA Position Type Full Time Job Description The Sr. Manager, Physical Design is the engineering leader who leads all aspects of physical design from RTL to GDSII. Experience leading multiple chips to tapeout from RTL to...
Sr. Director, SoC Architecture Location Los Gatos, CA Position Type Full Time Job Description The SoC Architect is the engineering leader who spearheads architecture of FPGA SoC and reports to VP of Silicon Engineering. Architect RapidSilicon’s FPGA SoC architecture...
Principal IP Verification Engineer Location San Jose, California Position Type Full Time Job Description The Principal IP Verification Engineer will set the technical direction for design verification actions Responsible for FPGA design verification at the IP and...
Principal IP P&R Engineer Location San Jose, California Position Type Full Time Job Description The Principal IP Design and Frontend Engineer will set the technical direction for the global IP P&R team Responsible for RTL to GDS implementation and signoff at...
Principal IP Design and Frontend Engineer Location San Jose, California Position Type Full Time Job Description The Principal IP Design and Frontend Engineer will set the technical direction for the global IP RTL Design team Responsible for FPGA RTL development at the...
Director, IP Verification Location San Jose, California Position Type Full Time Job Description The IP Verification Director will manage the global IP DV team Responsible for FPGA design verification at the IP and subsystem levels of hierarchy Ensure that the chip...
Dr. Naveed Sherwani is a well-known semiconductor industry veteran with over 30 years of entrepreneurial, engineering, and management experience. He is widely recognized as an innovator and leader in the field of design automation of ASICs and microprocessors and the main driver of the strategic evangelization of RISC-V International. Naveed has founded or co-founded over eleven silicon companies and raised over $850M in over 15 funding rounds from marquee venture capital firms during the course of his career. While serving as President, CEO, or Chairman, Naveed has been recognized as the leader of the “Most Respected Private Semiconductor Company” a record five times by the GSA (Global Semiconductor Alliance, the premier semiconductor industry membership body). He now serves as Chairman of GS Group, aiming to drive the next wave of silicon innovation by enabling growth strategies for semiconductor companies. Naveed also serves as the Chair the Open Source FPGA Foundation and is a Charter Member of notable Silicon Valley business forums such as TiE and OPEN. Dr. Naveed both a PhD and master’s degree in Computer Engineering at the University of Nebraska-Lincoln, and a BE degree at NED University in Karachi, Pakistan. Naveed has also authored several books and over 100 articles on various aspects of VLSI physical design automation and ASICs.
Prof. PE Gaillardon
15 years of innovation in the field of FPGA architectures and EDA tooling. Associate Professor and Associate Chair of Electrical and Computer Engineering (ECE) at The University of Utah and Principal Investigator of OpenFPGA. Recipients of prestigious NSP CAREER award, DARPA Young Faculty Award, IEEE CEDA Ernest Kuh award and ACM SIGDA ONFA award
20-year veteran of the FPGA industry with Xilinx, Altera and Intel. Expert in the strategic planning, product management, applications and marketing. Experienced as BU GM focusing on video, military, industrial and medical amongst others. Successfully defined and developed many key differentiating FPGA products and strategies for growth and disruption.
Alain Dargeles, Ph.D.
VP, EDA Software
Over 28 years of EDA experience, highly experienced in FPGA software stack, digital/analog design analysis, and verification/debugging. Earned his Ph.D. in Automatic Test Pattern Generation working concurrently for Compass Design Automation. Contributor to the open-source community in the space of SystemVerilog compilation. Alain holds several patents and published papers.
Dr. Xifan Tang
10-year experience in FPGA research and open-source EDA tool development. The leading developer and current code maintainer of the OpenFPGA project which has been adapted by several FPGA vendors. He was a Research Assistant Professor at the University of Utah. He has published 40 research papers, earned 1 best contribution award and hold 3 US patents.
VP, IP Engineering
A senior executive with over 30 years of experience in hardware and software development covering both senior technical and management roles. Darren’s work has focused on processor and FPGA design, EDA development for high-performance design, and the application of AI/ML. He holds both BSEE and MSEE degrees from Texas A&M University.
Bhavin Shah has worked in the semiconductor industry for over 25 years, with experience across all aspects of silicon development. At Rapid Silicon, he works as Senior Vice President of Engineering and leads all aspects of Engineering. Prior to joining Rapid Silicon, Bhavin was a part of Quantenna (acquired by onsemi), where he led WiFi-based IoT Client solutions and Access Point SoC development for 10+ years. Prior to Quantenna, Bhavin has held various engineering leadership and individual contributor positions in SoC development at Sibridge, Ikanos, VxTel, and eInfochips. Bhavin holds MSEE from San Jose State University and BSEE from Gujarat University.
VP, Business Development
Over 25 years of FPGA design, sales, marketing and management experience.
Launched the Cost-Optimized Portfolio and tripled product line opportunity funnels through several successful sales campaigns at Xilinx. Achieving over $1B in annual sales and 48% annual customer growth. Launched Xilinx's first SoC product, Zynq-7000, creating product positioning, training & marketing.
VP, HR & Corporate Affairs
Senior Human Resources professional with 20+ years of experience in high-technology. A demonstrated track record in many disciplines of HR including compensation, benefits, talent acquisition, immigration, coaching, and employee relations. A key member of the business leadership team and trusted advisor to C-level and senior managers.