Director, IP Design and Frontend


San Jose, California

Position Type

Full Time

Job Description

The IP Design and Frontend Director will manage the global IP RTL Design team

  • Responsible for FPGA RTL development at the IP/SS level
  • Ensure RTL ready for DV, P&R, SoC, and SW consumption
  • Establish high quality delivery culture across global IP team

Minimum Qualifications

  • B.S. in EE/CE/CS (M.S. preferred)
  • 12 years in chip development, 6 of those years RTL design
  • 3 years using a programming language, such as Python
  • Understands DV coverage, physical closure, and DFX flows
  • Experience coordinating projects and developing talent between local and remote teams

Preferred Skills

  • Developed an FPGA product; used an FPGA product
  • Have setup RTL lint, CDC/RDC, and SDC checks
  • Experience using a continuous integration system

Deadline to Apply

Drop us an email, with attached resume, to
*We’re an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status