Director, IP P&R
Location
Position Type
Job Description
- Responsible for RTL to GDS implementation and signoff at the IP/SS level
- Deliver timing and power models to SW team for customers
- Establish high quality delivery culture across global IP team
Minimum Qualifications
- B.S. in EE/CE/CS (M.S. preferred)
- 12 years in chip development, 6 of those years P&R
- 3 years using a scripting language, such as Tcl or Python
- Experience coordinating projects and developing talent between local and remote teams
- Understands contemporary manufacturing design rules
Preferred Skills
- Developed an FPGA product; used an FPGA product
- Understanding of packaging co-design and DFX flows
- Have setup IR/EM, LVS/DRC, DFM, and reliability checks