Floorplanning, IP Placement & Integrator Lead
Location
US, Canada, France, China
Position Type
Full Time
Job Description
As the Floorplanning and IP placement Lead you will oversee the development of RapidSilicon FPGA Floor planning and IP pre-placement solutions. Your global teams will be using open-source components and will contribute back to the open-source community. You will be responsible for selecting the best components, through rigorous evaluation, to base your development on. You will develop best-in-class floorplaning algorithms to pre-place large blocks consisting of hard and soft IPs along with data-path components. You will work with the GUI team to develop user-driven floorplanning and IP Integration capabilities.
Minimum Qualifications
- C. + 12 years or Ph.D. + 8 years of EDA Software experience
- 5 years of Floor planning and/or Placement algorithms development
- 5 years track record working with off-shore medium size teams
- 10 years of C++ and Design Patterns industry experience track record
Preferred Skills
- Experience with open-source development
- Experience with CI/CD development environments
Deadline to Apply
Rolling
Drop us an email, with attached resume, to careers@rapidsilicon.com
*We’re an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status