Principal IP Verification Engineer
Location
San Jose, California
Position Type
Full Time
Job Description
The Principal IP Verification Engineer will set the technical direction for design verification actions
- Responsible for FPGA design verification at the IP and subsystem levels of hierarchy
- Ensure that the chip functionality and the FPGA customer use-model are verified and consistent
- Development of testbench architecture and testplans
- Work with SoC level DV team for reuse of test collateral at SoC and system levels
- Provide technical guidance to worldwide IP DV team
Minimum Qualifications
- B.S. in EE/CE/CS (M.S. preferred)
- 12 years in chip development, 6 of those years in DV
- 5 years using a programming language, such as Python
- Hands on project experience using a UVM DV environment
- Experience coordinating projects and developing talent between local and remote teams
Preferred Skills
- Developed a UVM based testbench from scratch
- Developed an FPGA product; used an FPGA product
- Experience using a continuous integration system
Deadline to Apply
Rolling
Drop us an email, with attached resume, to careers@rapidsilicon.com
*We’re an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status