Senior ASIC Design Engineer


Salt Lake City, Utah / San Jose, CA

Position Type

Full Time

Travel Required


Job Description

Design and implementation of high-performance, low-power FPGA SoCs, including integration of analog and digital IPs from both internal and external vendors.
Write RTL design and debug of complex blocks in Verilog / System Verilog Analyze design and make implementation choices to optimize timing and power. Work with verification and physical design teams to achieve high quality design and successful tape-out.

Minimum Qualifications

  • Minimum BSc in CS/CE/EE or equivalent and 4 years of experience
  • ASIC design flow and direct experience with ASIC design in sub-28nm technology nodes
  • Experience in integrating IP from both internal and external vendors and the ability to specify and drive IP requirements in the physical domain.
  • Experience with large SoC designs (>20M gates) with frequencies in excess of 1GHz utilizing state of the art sub 45nm technologies.
  • Self-starter with strong communication and collaborative skills
  • Self-starter with strong communication and collaborative skills
  • From a CAD tool perspective, experience with floor planning tools, P&R flows, global timing verification and physical design verification flows
  • Familiarity with various process related design issues including design for yield and manufacturability, multi-Vt strategies and thermal management
  • Understanding of FPGA architecture and implementation is a plus

Deadline to Apply

Drop us an email, with attached resume, to
*We’re an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status