- Ms.C. + 15 years or Ph.D. + 10 years of EDA Software experience
- 5 years of compilation for SystemVerilog and VHDL RTL language and their corresponding LRMs.
- 5 years track record of managing off-shore medium size teams
- 10 years of C++ and design patterns industry experience track record
- Experience with open-source development
- Experience with CI/CD development environments