Synthesis Lead


US, Canada, France, China

Position Type

Full Time

Job Description

As the Synthesis Lead you will oversee the development of RapidSilicon’s FPGA synthesis solution. Your global teams will be using open-source components and will contribute back to the open-source community. You will be responsible for selecting the best components, through rigorous evaluation, to base your development on. You will select and implement a rigorous verification process that issimulation-based, formal verification-based and fuzzing-based. You will build an R&D team that is customer obsessed and provide fast turn-around-time on customer issues.

Minimum Qualifications

  • Ms.C. + 15 years or Ph.D. + 10 years of EDA Software experience
  • 5 years of compilation for SystemVerilog and VHDL RTL language and their corresponding LRMs.
  • 5 years track record of managing off-shore medium size teams
  • 10 years of C++ and design patterns industry experience track record

Preferred Skills

  • Experience with open-source development
  • Experience with CI/CD development environments

Deadline to Apply

Drop us an email, with attached resume, to
*We’re an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status