Timing Analysis Lead
US, Canada, France, China
As the Timing Analysis Lead, you will oversee the development of RapidSilicon’s FPGA timing analysis solution throughout the compiler stack. Your global teams will be using open-source components and will contribute back to the open-source community. You will be responsible for selecting the best components, through rigorous evaluation, to base your development on. You will report the progress on the quality of results achieved by the compiler and comprehensive roadmaps to the exec team. You will build an expert-level R&D and customer support team that will help customers achieve timing convergence with their designs.
- Ms.C. + 15 years or PhD + 10 years in EDA software experience
- 5 years of timing Analysis in ASIC and/or FPGA designs.
- 5 years of C++ and design patterns industry experience track record
- Experience with open-source development
- Experience with timing engine embedded in P&R Compiler stack
Deadline to Apply
Drop us an email, with attached resume, to firstname.lastname@example.org
*We’re an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status