How Rapid Silicon Shook Up the EDA Tools Industry with its Many Wins in the EPFL Combinational Suite Competition
An interview with Thierry Besson, Director of Software & EDA Synthesis at Rapid Silicon, and developer of the patent-pending ABC-DE algorithm
By Alain Dargelas, Vice President of Software Engineering at Rapid Silicon
The results of the latest École polytechnique fédérale de Lausanne (EPFL) Combinational Benchmark Suite competition are in. Rapid Silicon’s Raptor out-performed all leading EDA tools in the industry – by a lot! Raptor earned 24 unique wins and six tied wins out of a total of 40 benchmarks. That’s 30 best results out of 40! How is it that Raptor, the industry’s first and only commercial open-source FPGA design suite, broke the proverbial glass ceiling? The following Q&A with Rapid Silicon’s Theirry Besson, Director of Software & EDA Synthesis and the brain behind the patent-pending ABC-DE algorithm, reveals what’s different about Raptor and how it’s releasing the traditional tight control that FPGA companies have held over their EDA tools.
[Alain] Rapid Silicon’s strong showing in the EPFL Combinational Benchmark Suite competition show that Raptor performed 75% better than solutions from leading vendors and academia. Tell us, what prompted Rapid Silicon to compete against the industry leaders?
[Thierry] At Rapid Silicon, one of the central tenets is to proliferate open source for FPGAs. As an international open competition, the EPFL competition creates transparency for customers to do fair comparisons. Best results include LUT-6 count and logic levels for both size and performance efficiency. The competition gets progressively harder to improve best results as top-level universities and leading companies have been competing for several years. With our patent-pending technology, ABC-DE, we have been able to improve 24 benchmarks out of 40 and tie with the leader is six other benchmarks. We achieved some breakthrough results: some testcases showed a 3x reduction, some reached the absolute optimal result and some cases improved on designs that didn’t see any improvements for years. This demonstrates a clear jump in terms of quality of results.
[Alain] It seems Rapid Silicon’s patent-pending technology, ABC-DE, is a key differentiator. How does the technology work and what inspired you to create it?
[Thierry] ABC is an open-source logic synthesis tool that’s well-known in the EDA synthesis community. It gives decent results in terms of logic optimization/LUT mapping, but it’s not as good as commercial tools. My motivation was to improve the quality of results, so I introduced the Design Exploration (DE) concept. The DE extension builds on the ABC technology by adding dynamic mapping of the Boolean Logic. This exploration is AI-based and adaptive to the nature of the design, learning dynamically how to optimize the logic during the exploration process.
[Alain] Well, the results speak for themselves! I have one last question. You mentioned the EFPL is a very active competition. How will Rapid Silicon keep its place at the top?
[Thierry] Innovation, innovation, innovation! We’ve demonstrated a strong cutting-edge technology, but we need to keep watching the industry and learning from each other, and from competitions like the EPFL. Our goal is to continuously push, and this competition is a very reliable indicator of where we are versus academia and the industry. Moving forward, we have several avenues to pursue from partitioning strategies to furthering AI-based solutions. The opportunities to innovate are endless.
[Alain] Thank you, Thierry, for your thoughts and for the amazing work. It’s exciting to see such progress with open-source EDA software. All of us at Rapid Silicon are excited to be leading the way forward.