eFPGA IP
UNLEASH THE POWER OF PROGRAMMABILITY WITH VEGA eFPGA IP
Introducing Vega eFPGA IP, the flexible and efficient solution to enable programmable capabilities to your System on Chip (SoC)
Flexible and efficient solutions for SoC integration
The Vega eFPGA IP offers numerous benefits such as higher performance, reduced cost, IP protection, design assurance and compatibility, and IP security. It also comes with dedicated support for rapid implementation, a robust Raptor EDA tool with a large IP catalog, and easy SoC integration.
Vega is ready for evaluation NOW
(Within our Raptor EDA Tool)
Click below to download our product brief
configurable with different combinationsÂ
The Vega eFPGA IP has 3 types of configurable tiles – CLB, BRAM, and DSP. The CLB contains eight 6-input Lookup Tables (LUTs) with 2 independent outputs. It also supports a fast adder with a carry chain and shift register as an optional configuration mode.
The BRAM is 36Kb true dual port memory, which can be used as 18Kb split memory as well as different lower configurations.
The DSP MAC is an 18×20 multiplier with a 64-bit accumulator, which supports complex math functions implementations. The Vega eFPGA IP can be configured with different combinations of CLB, BRAM, and DSP tiles.
Key Advantages
- Higher performance
- Reduce cost
- Intellectual property protection
- Design assurance and compatibility
- Enable end customer flexibility and SW acceleration
- Dedicated support for rapid implementation
- Robust Raptor EDA tool with large IP catalog
- Easy SoC Integration
Key Features
- Customize Vega to suit your needs
- Accelerate your processor with Vega eFPGA
- Seamlessly integrate and verify Vega IP into your SoC design
- Enhance flexibility with on-chip FPGA functionality
- Program Vega with Raptor Design Suite
- Custom process portability
- Standard cell technology portable to any semiconductor fab
Interested in CXL 3.0 IP?
Click below to learn more
Contact us
Contact us today to learn more about our Vega eFPGA IP and how it can benefit your design