CAD Methodology Engineer (Stuff/Principal)


San Jose, California

Position Type

Full Time

About Us

At RapidSilicon, we focus on bringing creativity to FPGA design by combining open-source FPGA methodology with proprietary technologies that enable a faster design-to-silicon turnaround. Our employees work on innovative AI-enhanced EDA tools to provide the most optimized design result that satisfies the needs in general-purpose or domain-specific applications.

To view our job listings, please visit our Careers page at

Job Description

The CAD Methodology Engineer will set the technical direction for the global VLSI R&D Team

  • Responsible for corporate CAD/EDA flow and Methodology from front to backend
  • Develop CAD/EDA flow and methodology for ASIC and FPGA Design
  • Establish high quality delivery culture across global IP and ASIC team

Minimum Qualifications

  • BS/MS in EE/CE/CS (M.S. preferred)
  • 10+ years of experience on CAD/EDA Flow and Methodology development
  • Proficient in scripting languages, such as Tcl, Python, Perl and c-shell
  • Experience in developing Makefile
  • Understands contemporary manufacturing design rules

Preferred Skills

  • Developed CAD tool flow such as, Synopsys, Cadence, Mentor and Xilinx from front to backend
  • Understanding of packaging co-design and DFX flows
  • Proficient in setting up tools and flows on Analog/Mixed Signal Environment, RTL Design and Verification, Synthesis, Place and Route, Timing, IR/EM, LVS/DRC, DFM, and reliability checks

Deadline to Apply

Drop us an email, with attached resume, to
*We’re an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status