Raptor Design Suite, What’s in It for You?
By Alain Dargelas, Ph.D., Vice President of Software Engineering
Welcome to our in-depth exploration of the newly released Raptor Design Suite, now available as a fully open-source platform. Let’s delve into the specifics of the SDK.
In essence, Raptor is a complete RTL to Bitstream Compiler that has been fully validated, including its packaged IP Portfolio and Simulation models, using thousands of benchmarks and test cases running in Continuous Integration.
We consider it as a complete design suite as FPGA designers will find it includes all the components necessary to complete their design from initial RTL coding to debugging and deploying in the field onto the FPGA hardware. Additionally, it comes with comprehensive documentation, the Raptor User Guide, complete with clear examples.
To this end, within the Raptor package, we’ve compiled various open-source components using a unified build, test, and release system:
- Synthesis: Yosys (augmented with SystemVerilog and VHDL plugin parsers)
- Partitioner, Place&Route: Mt-kahypar, VPR
- Bitstream generation: OpenFPGA
- Simulators: IVerilog, Verilator
- Waveform Viewer: Gtkwave
- IP Generator: LiteX
- Programmer: Openocd
- License manager: OpenLM
- GUIs: FOEDAG, Monaco-editor integration (Contribution from QuickLogic), Teros-HDL, ProgrammerGui
Optional with subscription, a built-in AI assistant that can run on premises or on the cloud: RapidGPT
Additionally, Raptor includes numerous utilities such as Encryption, Tcl, Python, Device Modeling and Installer. The list of components continue to expand as we actively seek and incorporate new functionalities. We have also published (public fork) or merged upstream the changes we’ve made to these components, including optimizations and bug fixes.
As an end-user, you have two options: compile Raptor from scratch on your machine for a guaranteed result and receive continuous updates or download our quarterly refreshed Raptor Release. This release includes all precompiled components mentioned earlier, along with actual FPGA models manufactured by Rapid Silicon and our benchmark-winning Boolean Optimizer ABC-DE. A basic version of the patent-pending optimizer is also available in the open-source repository.
You can leverage our Qualified IP Portfolio, Bring or Develop from scratch your own RTL (SystemVerilog, Verilog and VHDL), Simulate conveniently at every stage of the flow, Debug, Generate bitstream, Program the device and Debug On Chip using our debug IP.
The open-source nature or Raptor offers transparency to the user, enhances debuggability, removes security concerns associated with installing a foreign set of executables on your system, eliminates the stress of EOL concerns, and encourages greater feedback and contribution from users and other FPGA vendors.
Stay tuned for more updates on our open-source release!