Sr. Manager, SoC Design
At RapidSilicon, we focus on bringing creativity to FPGA design by combining open-source FPGA methodology with proprietary technologies that enable a faster design-to-silicon turnaround. Our employees work on innovative AI-enhanced EDA tools to provide the most optimized design result that satisfies the needs in general-purpose or domain-specific applications.
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• Build, manage and mentor ASIC front end teams responsible for an SoC-FPGA design. Drive Design planning, microarchitecture development and design execution.
• Review micro-architecture and design to meet architecture spec and optimize Power, Performance and Area. Drive key metrics and milestones to meet silicon tape out schedule.
• Communicate efficiently between design teams, logic, process, product / test engineering and architecture teams.
• Ability to provide mentorship and guidance to team members.
• Work closely with DV team in reviewing test plans, and fixing design issues optimally.
• Ensure resourcing is aligned to meet execution deliverables.
• Define, implement, and maintain key performance indicators (KPI) for areas of responsibility.
• M.S. or Ph.D. in Electrical/Computer Engineering or related technical field
• 12+ years of experience in managing ASIC/SoC design teams and working across multiple projects.
• 7+ years of experience in managing front-end design team.
• Experience with multiple successful ASIC tape outs. Track record of first-pass success
• Experienced with interpreting functional specs and developing architecture, microarchitecture and logic design.
• Clear understanding of state-of-the-art design flows, design and verification methodologies
• Proficiency in RTL design, DFT, synthesis, timing closure, SoC integration and verification.
• A strong leader with experience in working with a distributed team.