Sr./Principal Engineer FPGA P&R
At RapidSilicon, we focus on bringing creativity to FPGA design by combining open-source FPGA methodology with proprietary technologies that enable a faster design-to-silicon turnaround. Our employees work on innovative AI-enhanced EDA tools to provide the most optimized design result that satisfies the needs in general-purpose or domain-specific applications.
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Expertise in FPGA Place and Route, Static Timing Analysis are required. In this role you’ll define the roadmap to improve the Quality of Results, compile time and memory requirements of the Rapid Silicon compiler backend solution.
Your ability to navigate multi-million lines source code base, both open and close source, define code restructuring tasks, evaluate different open-source components for readiness and integration into an industrial strength software will make you an invaluable asset to the fast-paced, dynamic FPGA Software R&D team.
- Expert-level C++
- Structural Verilog
- Synopsys Design Constraints
- Static Timing Analysis
- FPGA Place and Route algorithms (Simulated annealing, Analytical placer, Routing algorithms)
- Troubleshooting experience in Timing Convergence issues.
- CI/CD (Github Workflows)