At RapidSilicon, we focus on bringing creativity to FPGA design by combining open-source FPGA methodology with proprietary technologies that enable a faster design-to-silicon turnaround. Our employees work on innovative AI-enhanced EDA tools to provide the most optimized design result that satisfies the needs in general-purpose or domain-specific applications.

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• Define, implement, and verify DFT architecture and features for Scan / MBIST / JTAG / ATPG / boundary-scan.
• Setup DFT development methodologies, plans, and schedules.
• ATPG patterns verification with gate-level simulation.
• Decide the tradeoff of test coverage and test cost.
• Support post-silicon bring-up and yield analysis.

• Master with at least 6 years or Bachelor with at least 8 years demonstrated experience in DFT for VLSI designs.
• Expert in scan insertion, ATPG, MBIST, JTAG, boundary scan, Scan Compression, and at-speed testing.
• Engagement with Design teams on pre-Silicon test planning and validation.
• Excellent debugging skills for RTL and gate-level simulations.
• Good communication skills and the ability to work with teams crossing different geos.
• Knowledge of defect types, fault models, debugging, and validation on ATE and silicon bring-up.
• Proven leadership skills.