Sr. Staff Engineer, Floorplan & Integration
Citizen / PR (should not require any immigration services)
At RapidSilicon, we focus on bringing creativity to FPGA design by combining open-source FPGA methodology with proprietary technologies that enable a faster design-to-silicon turnaround. Our employees work on innovative AI-enhanced EDA tools to provide the most optimized design result that satisfies the needs in general-purpose or domain-specific applications.
To view our job listings, please visit our Careers page at rapidsilicon.com/careers/
Key Responsibilities for this position include but not limited to:
- Perform SOC full chip physical design; floor-planning, I/O, bump & RDL (Redistribution layer) planning, hard IP integration, partitioning, power/ground grid generation, pin assignment, partition hardening, chip-level clock, feedthrough, special interface, and interconnect planning, bus routing, sequential pipeline planning and full-chip design for testability (DFT) planning
- Collaborate with chip architects, package engineers, and block PD owners to drive, chip floorplan reviews and identify area, interconnect, IP integration, and floorplan improvement opportunities
- Work with STA, PV, RV, and other signoff teams to achieve closure and tapeout on time
- Run physical verification at chip-level and provide feedback and guidance to block-level physical design engineers to fix design rule check/layout versus schematic/antenna/electrical rule check/design for manufacturing violations
- Develop/modify design flows as needed to meet the overall design quality of results and chip integration requirements
- Master with at least 6 years or Bachelor with at least 8 years design experience in the structural/physical design domain
- Have multiple tape-out experience in deep submicron, preferably experience in 14nm and below
- Proficient in aspects of physical design from RTL hand-off through streaming out a clean GDSII (such as Floorplan, Synthesis, Auto Place & Route, Signal Integrity Verification, Clock Tree Synthesis, Performance Verification, Reliability Verification, Power Analysis & Optimisation, Timing Closure etc).
- Experience in relevant VLSI structural/physical design methodology, flows and relevant EDA tools will be an advantage
- Experience in Block-level Implementation and Full-chip floor-planning and power grid planning.
- Previous experience as a key technical leading role in development and delivery of leading edge physical databases for ASICs, SoCs or IPs will be an advantage
- Experienced in industry RTL to GDSII tools: Design Compiler, IC Compiler II, Fusion Compiler, PrimeTime, etc
- Hands-on expertise with scripting languages such as Perl, TCL, and knowledge of hardware description languages of VHDL & Verilog.
- Possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment.