Sr. Staff Engineer, Physical Verification


Penang, Malaysia

Position Type

Full Time

Immigrant Status

Citizen / PR (should not require any immigration services)

Travel Required


About Us

At RapidSilicon, we focus on bringing creativity to FPGA design by combining open-source FPGA methodology with proprietary technologies that enable a faster design-to-silicon turnaround. Our employees work on innovative AI-enhanced EDA tools to provide the most optimized design result that satisfies the needs in general-purpose or domain-specific applications.

To view our job listings, please visit our Careers page at

Job Description

You will be directly involved in hardening of the SOC partitions that will be integrated with Rapid Silicon’s next-generation FPGA products. You will have the opportunity to work on partitions like RISC-V, ARM, Memory subsystem, PCIE subsystem, etc.
Key Responsibilities for this position include but not limited to:
  • Take the leadership role of developing and supporting block and full chip automated physical verification flows and scripts
  • Perform block and full-chip physical verification and work with the physical design team to close design issues
  • Work with the PD team to clean up all DRC/LVS/ESD/ERC/ANT violations and sign off PV for tapeouts
  • Work closely with semiconductor foundries on installation, and maintenance of process design kits (PDKs) for SOC physical design teams
  • Design custom circuits for some analog and/or high-speed circuits

Minimum Qualifications

  • Master with at least 6 years or Bachelor with at least 8 years design experience in the structural/physical design domain
  • Have multiple tape-out experience in deep submicron, preferably experience in 14nm and below
  • Experience working with block or full chip physical verification and/or owning Physical Verification CAD flow development and support
  • Experience in relevant VLSI structural/physical design methodology, flows and relevant EDA tools will be an advantage

Preferred Skills

  • Previous experience as a key technical leading role in development and delivery of leading edge physical databases for ASICs, SoCs or IPs will be an advantage
  • Experienced in industry RTL to GDSII tools: Design Compiler, IC Compiler II, Fusion Compiler, PrimeTime, etc
  • Hands-on expertise with scripting languages such as Perl, TCL, and knowledge of hardware description languages of VHDL & Verilog.
  • Possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment.

Deadline to Apply

Drop us an email, with attached resume, to
*We’re an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status