Sr. Staff Engineer, Reliability Verification
Citizen / PR (should not require any immigration services)
At RapidSilicon, we focus on bringing creativity to FPGA design by combining open-source FPGA methodology with proprietary technologies that enable a faster design-to-silicon turnaround. Our employees work on innovative AI-enhanced EDA tools to provide the most optimized design result that satisfies the needs in general-purpose or domain-specific applications.
To view our job listings, please visit our Careers page at rapidsilicon.com/careers/
Key Responsibilities for this position include but not limited to:
- Work with the DA team to define the Reliability Verification (RV) methodology.
- Provide guidance to the design team to build a strong reliable design.
- Support PDN, Electromigration/IR-drop (EMIR), Self-heat, ESD, Latch-up, and PERC flows.
- Drive solutions for all RV issues and violations.
- Tightly collaborate with the design and DA team on issue resolution.
- Master with at least 6 years or Bachelor with at least 8 years design experience in the structural/physical design domain
- Have multiple tape-out experience in deep submicron, preferably experience in 14nm and below
- In-depth knowledge in silicon reliability issues such as EMIR, Self-heat, ESD, Latch-up, Aging, etc.
- Good knowledge of high-speed IO (DDR/SerDes) design and reliability challenges.
- Must have solid experience with industry CAD tools in reliability and physical design –Apache Redhawk/Totem/Pathfinder, Calibre/ICV, Cadence Voltus/VoltusFi, etc.
- Experienced in industry RTL to GDSII tools: Design Compiler, IC Compiler II, Fusion Compiler, PrimeTime, etc
- Hands-on expertise with scripting languages such as Perl, TCL, and knowledge of hardware description languages of VHDL & Verilog.
- Expertise in SOC design methodology, design automation, and full-chip signoff.
- Possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment.