Citizen / PR (should not require any immigration services)

At RapidSilicon, we focus on bringing creativity to FPGA design by combining open-source FPGA methodology with proprietary technologies that enable a faster design-to-silicon turnaround. Our employees work on innovative AI-enhanced EDA tools to provide the most optimized design result that satisfies the needs in general-purpose or domain-specific applications.

To view our job listings, please visit our Careers page at rapidsilicon.com/careers/

• You will be directly involved in hardening of the SOC partitions that will be integrated with Rapid Silicon’s next-generation FPGA products. You will have the opportunity to work on partitions like RISC-V, ARM, Memory subsystem, PCIE subsystem, etc.
• You will be leading a team of engineers who will be taking the blocks through the RTL-to-GDS flow (Synthesize, Floorplan, APR and signoff).
• You will be expected to perform various quality check to ensure signoff (timing, physical verification, IR drop, Functional Equivalence check) requirements are met. This includes analyzing reports and utilize scripts to debug, automate tasks and provide feedback to relevant stakeholders.
• You will also need to drive implementation requirements Influence & Continuous seek to improve the RTL to GDSII methodology
• In the process you will be working closely with Architecture and Design team to understand, address and converge partition.

• Master with at least 6 years or Bachelor with at least 8 years design experience in the structural/physical design domain
• Have multiple tape-out experience in deep submicron, preferably experience in 14nm and below
• Proficient in aspects of physical design from RTL hand-off through streaming out a clean GDSII (such as Floorplan, Synthesis, Auto Place & Route, Signal Integrity Verification, Clock Tree Synthesis, Performance Verification, Reliability Verification, Power Analysis & Optimisation, Timing Closure etc).
• Experience in relevant VLSI structural/physical design methodology, flows and relevant EDA tools will be an advantage
• Experience in Block-level Implementation and Full-chip floor-planning and power grid planning.

• Previous experience as a key technical leading role in development and delivery of leading edge physical databases for ASICs, SoCs or IPs will be an advantage
• Experienced in industry RTL to GDSII tools: Design Compiler, IC Compiler II, Fusion Compiler, PrimeTime, etc
• Hands-on expertise with scripting languages such as Perl, TCL, and knowledge of hardware description languages of VHDL & Verilog.
• Possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment.