At RapidSilicon, we focus on bringing creativity to FPGA design by combining open-source FPGA methodology with proprietary technologies that enable a faster design-to-silicon turnaround. Our employees work on innovative AI-enhanced EDA tools to provide the most optimized design result that satisfies the needs in general-purpose or domain-specific applications.

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As a senior Reliability Verification engineer, you need:

• Work with the DA team to define the Reliability Verification (RV) methodology.
• Provide guidance to the design team to build a strong reliable design.
• Support PDN, Electromigration/IR-drop (EMIR), Self-heat, ESD, Latch-up, and PERC flows.
• Drive solutions for all RV issues and violations.
• Tightly collaborate with the design and DA team on issue resolution.

• BSEE/MSEE and at least 7 years of experience in design and design automation-related fields.
• Experience of providing design for reliability guidance throughout the development process.
• In-depth knowledge in silicon reliability issues such as EMIR, Self-heat, ESD, Latch-up, Aging, etc.
• Good knowledge of high-speed IO (DDR/SerDes) design and reliability challenges.
• Must have solid experience with industry CAD tools in reliability and physical design –Apache Redhawk/Totem/Pathfinder, Calibre/ICV, Cadence Voltus/VoltusFi, etc.
• Expertise in SOC design methodology, design automation, and full-chip signoff.
• Proficiency in scripting languages such as Tcl, Perl, Python.
• Independent, Self-motivated, excellent communication skills, and good team player.