At RapidSilicon, we focus on bringing creativity to FPGA design by combining open-source FPGA methodology with proprietary technologies that enable a faster design-to-silicon turnaround. Our employees work on innovative AI-enhanced EDA tools to provide the most optimized design result that satisfies the needs in general-purpose or domain-specific applications.

To view our job listings, please visit our Careers page at rapidsilicon.com/careers/   

As a senior timing engineer, you need:

• • Set up the timing constraints, and help to define the overall static timing analysis methodology
  • Set up the static timing analysis infrastructure and sign-off convergence flows.
  • Drive IP and full-chip level timing closure for SoC/FPGA projects.
  • Drive solutions for critical timing paths by collaborating with backend, logic, floorplan, and other relevant owners.
  • Build timing and power models for our software team.
  • Provide technical leadership and collaborate across teams to come up with the best solution possible with a One Microsoft mindset.
  • Apply your growth mindset to learn and adapt to a dynamic environment.

• Candidate must have at least a bachelor’s degree in Electrical Engineering or Computer Engineering with 8+ years of experience.
• Solid experience with EDA tools such as Static Timing Analysis, Noise Glitch analysis, and interconnect extraction.
• Have done at least 3 successful tapeouts.
• Experience in managing timing constraints, exceptions, IP constraint promotion, etc.
• Solid experience in transistor and gate-level static timing and noise analysis

• Proficiency in scripting languages such as Tcl, Perl, Python.
• Independent, Self-motivated, excellent communication skills, and good team player.