At RapidSilicon, we focus on bringing creativity to FPGA design by combining open-source FPGA methodology with proprietary technologies that enable a faster design-to-silicon turnaround. Our employees work on innovative AI-enhanced EDA tools to provide the most optimized design result that satisfies the needs in general-purpose or domain-specific applications.

To view our job listings, please visit our Careers page at rapidsilicon.com/careers/   

• Perform SOC full chip physical design; floor-planning, I/O, bump & RDL (Redistribution layer) planning, hard IP integration, partitioning, power/ground grid generation, pin assignment, partition hardening, chip-level clock, feedthrough, special interface, and interconnect planning, bus routing, sequential pipeline planning and full-chip design for testability (DFT) planning
• Collaborate with chip architects, package engineers, and block PD owners to drive, chip floorplan reviews and identify area, interconnect, IP integration, and floorplan improvement opportunities
• Work with STA, PV, RV, and other signoff teams to achieve closure and tapeout on time
• Run physical verification at chip-level and provide feedback and guidance to block-level physical design engineers to fix design rule check/layout versus schematic/antenna/electrical rule check/design for manufacturing violations
• Develop/modify design flows as needed to meet the overall design quality of results and chip integration requirements

• Bachelor’s degree in electrical engineering, computer engineering or computer science
• 8+ years of ASIC full-chip tapeout and/or physical design flow development experience
• Self-driven individual with a can-do attitude, and an ability to work in a dynamic group environment with remote time zones
• Excellent scripting skills (csh/bash, Perl, Python TCL, Makefile etc.)
• In-depth knowledge of industry-standard EDA tools, understanding their capabilities and underlying algorithms